Wafer in-line/kerf testing is a common step in wafer process yield monitoring. Wafer testing is the process of testing integrated circuits at the wafer level while the individual chips (i.e., die) are contained in a wafer, e.g., prior to dicing and packaging the individual chips. In-line testing, also referred to as in-process testing, is performed between fabrication steps at the wafer level using test equipment including wafer probes. The probes are used to establish contact with locations on the wafer for providing electric power to circuits contained in the chips for testing the chips, e.g., for defects. The locations on the wafer where the probes contact the wafer can be within the individual die, or may be in the kerf lines (i.e., interstitial areas) between the die.
Current in-line/kerf testing uses cantilever-type probe sets, which provide fine-pitch probing and work well for direct current (DC) and analog signals. Cantilever-type probe sets typically operate at low power and have long lead lengths that are not suited to radio frequency (RF) signals.
Manual probing, in contrast to in-line testing, is where a wafer is taken out of the process line and manually tested. Manual RF probe sets, e.g., including some ground-signal-ground (GSG) probe sets, may be used for some RF tests. However, such manual probing is time and labor intensive compared to in-line testing, and normally is confined to testing at the last metal layer of the wafer (e.g., the last wiring level of the wafer) in order to avoid damaging the dielectric layers when being used for thin metal probing.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.